10. CACHE Instructions
10.19 Index Load Data (S)
Index Load Data (S) loads a doubleword of data and all 10 check bits into the CP0 TagHi, TagLo, and ECC registers. The address of the target doublewords comes from the PA of the CACHE instruction. The way comes from PA[0] of the CACHE instruction. The high word will be loaded into CP0 TagHi and the low word of data will be loaded into CP0 TagLo. The check bits will be loaded into CP0 ECC[9:0]. The MRU field is unmodified.
ECC correction and checking is suppressed during Index Load Data (S).
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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